#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
/* USB gadget RNDIS */
#endif
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
#endif
-#endif /* !CONFIG_NAND */
+#endif /* !CONFIG_MTD_RAW_NAND */
/*
* For NOR boot, we must set this to the start of where NOR is mapped
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
#elif defined(CONFIG_EMMC_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_SYS_MMC_MAX_DEVICE 2
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* SPI flash. */
/* Network. */
-#define CONFIG_PHY_SMSC
/* Enable Atheros phy driver */
-#define CONFIG_PHY_ATHEROS
/*
* NOR Size = 16 MiB