+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Timesys Corporation
* Copyright (C) 2016 Advantech Corporation
* Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ADVANTECH_DMSBA16_CONFIG_H
#define CONFIG_LBA48
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_BOUNCE_BUFFER
/* USB Configs */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* Networking Configs */
#define CONFIG_FEC_MXC
-#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
/* Serial Flash */
#ifdef CONFIG_CMD_SF
-#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */