*/
#define CONFIG_USE_INTERRUPT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
-#define CONFIG_ARCH_MAP_SYSMEM
-
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SERVERIP
-
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
#endif
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
* Size of malloc() pool
*/
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* Physical Memory Map
GENERATED_GBL_DATA_SIZE)
/*
- * Load address and memory test area should agree with
- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-/* memtest works on 63 MB in DRAM */
-
-/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
/* support JEDEC */
-#ifdef CONFIG_CFI_FLASH
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
-#endif
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
-#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */