+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
*/
#define CONFIG_USE_INTERRUPT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_PANIC_HANG
-
-#define CONFIG_ARCH_MAP_SYSMEM
-
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SERVERIP
-
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
#endif
-#else
-
-#define CONFIG_SYS_TEXT_BASE 0x80000000
#endif
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
*/
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER 1
-#define CONFIG_FTSDC010_SDIO
-
-/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
/*
* Size of malloc() pool
*/
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* Physical Memory Map
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
-#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
-
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
GENERATED_GBL_DATA_SIZE)
/*
- * Load address and memory test area should agree with
- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x300000
-
-/* memtest works on 63 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
-
-/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
* FLASH and environment organization
*/
/* use CFI framework */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
/* support JEDEC */
-#ifdef CONFIG_CFI_FLASH
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
-#endif
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
-#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_OFFSET 0x140000
-#define CONFIG_ENV_SIZE 8192
-#define CONFIG_ENV_OVERWRITE
/* SPI FLASH */
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#define CONFIG_SF_DEFAULT_MODE 0
/*
* For booting Linux, the board info and command line data