#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CPU_ID_STR "MPC8265"
#define CONFIG_CPM2 1 /* Has a CPM2 */
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
#define BCSR_PCI_MODE 0x01
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif