Makefile: move all Power Architecture boards into boards.cfg

[platform/kernel/u-boot.git] / include / configs / WUH405.h

diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 01cdf3a..3ca19fc 100644 (file)
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -38,6 +38,8 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_WUH405          1       /* ...on a WUH405 board         */
 
+#define        CONFIG_SYS_TEXT_BASE    0xFFFC0000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
 #define CONFIG_MISC_INIT_R     1       /* call misc_init_r()           */
 
@@ -58,6 +60,7 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
@@ -121,10 +124,14 @@
 #define CONFIG_SYS_MEMTEST_START       0x0400000       /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 
+#define CONFIG_CONS_INDEX      2       /* Use UART1                    */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
-#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 #define CONFIG_SYS_BASE_BAUD       691200
-#define        CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      \
@@ -147,7 +154,6 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define NAND_MAX_CHIPS          1
 #define CONFIG_SYS_MAX_NAND_DEVICE     1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US      25
 
@@ -242,6 +248,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
@@ -332,12 +339,12 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000550
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_OSRL          0x40000550
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 #define CONFIG_SYS_GPIO0_TCR           0xF7FE0014
 
 #define CONFIG_SYS_DUART_RST           (0x80000000 >> 14)