ppc4xx: Big header cleanup part 2, mostly PPC405 related

[platform/kernel/u-boot.git] / include / configs / VOM405.h

diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index b6e3588..747d6a0 100644 (file)
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -53,6 +53,7 @@
 #define CONFIG_NET_MULTI       1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -120,7 +121,6 @@
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
-#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 #define CONFIG_SYS_BASE_BAUD       691200
 #undef CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
@@ -177,10 +177,10 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_FLASH_BASE          0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN          (256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT            1
@@ -203,6 +203,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
@@ -231,8 +232,7 @@
 /*
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
-#define CONFIG_SYS_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR   0xfffc0000
 
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
@@ -273,12 +273,12 @@
 /* GPIO Output:                OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000500  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L         0x14000045  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL          0x40000500  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H         0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TCR           0xF7FE0014  /*  0 ... 31 */
 
 /*
@@ -293,17 +293,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
-#define PLLMR0_DEFAULT  PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT  PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT  PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT  PLLMR1_200_100_50_33
-#endif
-#if 1
 #define PLLMR0_DEFAULT  PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT  PLLMR1_133_66_66_33
-#endif
 
 #endif /* __CONFIG_H */