/*
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2003
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Gary Jennejohn <gj@denx.de>
#define __CONFIG_H
/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_INIT_CRITICAL /* undef for developing */
-
-/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_CACHE | \
+ /*CFG_CMD_JFFS2 |*/ \
+ /*CFG_CMD_NAND |*/ \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
+ CFG_CMD_USB | \
CFG_CMD_REGINFO | \
+ CFG_CMD_FAT | \
+ CFG_CMD_DATE | \
CFG_CMD_ELF | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
CFG_CMD_BSP)
/* this must be included after the definiton of CONFIG_COMMANDS */
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
+/*#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)*/
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_MONITOR_LEN (256 * 1024)
-#define CFG_MALLOC_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
/*
* Hardware drivers
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_KEYBOARD 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0 1
+
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
+
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.0.110
#define CONFIG_SERVERIP 10.0.0.1
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
-#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+#define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
+
#define CFG_ALT_MEMTEST
-#define CFG_LOAD_ADDR 0x33000000 /* default load address */
+#define CFG_LOAD_ADDR 0x30800000 /* default load address */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* support BZIP2 compression */
+#define CONFIG_BZIP2 1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+/*#define VERSION_TAG "released"*/
+#define VERSION_TAG "unstable"
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
+
/*-----------------------------------------------------------------------
* Stack sizes
*
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#endif
-#define MULTI_PURPOSE_SOCKET_ADDR 0
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand) NF_WaitRB()
+
+#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
+
+
+#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
+#define WRITE_NAND(d, adr) NF_Write(d)
+#define READ_NAND(adr) NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_MTD_NAND_ECC_JFFS2 1
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
#endif /* __CONFIG_H */