#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
-#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
+#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
/* (it will be used if there is no */
/* 'cpuclk' variable with valid value) */
-#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
- /* (function measure_gclk() */
- /* will be called) */
-#ifdef CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
-#endif
-
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "bootfile=/tftpboot/TQM885D/uImage\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
+ "ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
# define CONFIG_RTC_DS1337 1
# define CFG_I2C_RTC_ADDR 0x68
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
+#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
/*
* Miscellaneous configurable options
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
- * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
- * Memory Periodic Timer Prescaler
- * Periodic timer for refresh, start with refresh rate for 40 MHz clock
- * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ * CPUclock(MHz) * 31.2
+ * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
+ * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
+ * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
+ * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
+ * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
*/
-#define CFG_MAMR_PTA 39
+#define CFG_MAMR_PTA 128
/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
*/
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_CMD_MII)
#define CFG_DISCOVER_PHY
+#define CONFIG_MII_INIT 1
#endif
#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
projects / platform / kernel / u-boot.git / blobdiff