#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#if defined(CONFIG_TQM8548_BE)
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xfffc0000
+#endif
+
#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
#define CONFIG_TQM8548
#endif
* NAND flash support (disabled by default)
*
* Warning: NAND support will likely increase the U-Boot image size
- * to more than 256 KB. Please adjust TEXT_BASE if necessary.
+ * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
*/
#ifdef CONFIG_TQM8548_BE
#define CONFIG_NAND
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x10000000
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR 0xA0000000
+#else
+#define CONFIG_SYS_CCSRBAR 0xE0000000
+#endif
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+
+#if defined(CONFIG_TQM_BIGFLASH) || \
+ (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
+#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
+#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512)
+#else
+#define CONFIG_SYS_PPC_DDR_WIMGE (0)
+#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024)
+#endif
+
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
-#define CONFIG_DDR_DLL /* DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/*
* Note: when changing the Local Bus clock divider you have to
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
+ 0x04010000) /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */
#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
/* Serial Port */
#else /* !CONFIG_TQM8560 */
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCIE1
* Addresses are mapped 1-1.
*/
#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
-#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
#endif /* CONFIG_PCIE1 */
#endif /* CONFIG_PCI */
-#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
MK_STR(CONFIG_HOSTNAME)".dtb\0"
#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
- "uboot_addr="MK_STR(TEXT_BASE)"\0"
+ "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_ENV_BOOTFILE \
projects / platform / kernel / u-boot.git / blobdiff