#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
/*
* sysclk for MPC85xx
*
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x10000000
-
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
/*
* DDR Setup
*/
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
#endif
-
/*
* Flash on the Local Bus
*/
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#undef CONFIG_MPC85XX_TSEC1
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#undef CONFIG_MPC85XX_FEC
-#define FEC_PHY_ADDR 0
+#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
+#define FEC_PHY_ADDR 2
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "ENET1"
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC1"
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
ADD_PCI_CMD | \
- CFG_CMD_PING | \
- CFG_CMD_I2C )
+ CFG_CMD_I2C | \
+ CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */