/*
* Copyright 2005 DENX Software Engineering
+ * Wolfgang Denk <wd@denx.de>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
#undef CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-
/*
* sysclk for MPC85xx
*
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x10000000
-
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
/*
* DDR Setup
*/
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
#endif
-
/*
* Flash on the Local Bus
*/
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#undef CONFIG_MPC85XX_TSEC1
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#undef CONFIG_MPC85XX_FEC
-#define FEC_PHY_ADDR 0
+#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_MPC85XX_FEC_NAME "FEC"
+#define FEC_PHY_ADDR 2
#define FEC_PHYIDX 0
-#define CONFIG_ETHPRIME "MOTO ENET2"
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME "TSEC1"
#endif /* CONFIG_TSEC_ENET */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
+ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
+ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
+# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP )
+#endif
+
+#if defined(CONFIG_PCI)
+# define ADD_PCI_CMD (CFG_CMD_PCI)
#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+# define ADD_PCI_CMD 0
#endif
+#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
+ ADD_PCI_CMD | \
+ CFG_CMD_I2C | \
+ CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"bootfile=/tftpboot/tqm8540/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "kernel_addr=FE000000\0" \
+ "ramdisk_addr=FE100000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"