configs: move CONFIG_SPL_TEXT_BASE to Kconfig
[platform/kernel/u-boot.git] / include / configs / T4240RDB.h
index f5eed09..a818f0c 100644 (file)
@@ -21,7 +21,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
 #else
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
 #define CONFIG_SPL_PAD_TO              0x40000
 #define CONFIG_SPL_MAX_SIZE            0x28000
 #define RESET_VECTOR_OFFSET            0x27FFC
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
-#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 
 #define CONFIG_DDR_SPD
 
        "bootm 0x01000000 - 0x00f00000"
 
 #if defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_SPI_BUS              0
-#define CONFIG_ENV_SPI_CS               0
-#define CONFIG_ENV_SPI_MAX_HZ           10000000
-#define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
@@ -460,7 +454,7 @@ unsigned long get_board_ddr_clk(void);
                                | CSPR_MSEL_GPCM \
                                | CSPR_V)
 
-#define CONFIG_SYS_AMASK3      IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3      IFC_AMASK(64 * 1024)
 #define CONFIG_SYS_CSOR3       0x0
 
 /* CPLD Timing parameters for IFC CS3 */
@@ -508,8 +502,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_SF_DEFAULT_SPEED         10000000
-#define CONFIG_SF_DEFAULT_MODE          0
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN