Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI

[platform/kernel/u-boot.git] / include / configs / T4240RDB.h

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 0486264..87e3e67 100644 (file)
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -18,7 +18,6 @@
 #define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */
 
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
 #ifndef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
@@ -38,7 +37,6 @@
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
 #endif
 
 #ifdef CONFIG_SPL_BUILD
@@ -130,7 +128,6 @@
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN         (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -208,7 +205,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 
 /*
  * For booting Linux, the board info and command line data
@@ -218,10 +214,6 @@
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
-#endif
-
 /*
  * Environment Configuration
  */
@@ -292,7 +284,6 @@ unsigned long get_board_sys_clk(void);
                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_MAX_ECCPOS     256
 #define CONFIG_SYS_NAND_MAX_OOBFREE    2
 #define CONFIG_SYS_NAND_BASE           0xff800000
@@ -313,8 +304,6 @@ unsigned long get_board_sys_clk(void);
                                | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
                                | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
                                        FTIM0_NAND_TWP(0x18)   | \
@@ -333,8 +322,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
-
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
@@ -483,8 +470,6 @@ unsigned long get_board_sys_clk(void);
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_FMAN_FW_ADDR        (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR        (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_FMAN_FW_ADDR        0xEFF00000
 #endif