Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / include / configs / T4240QDS.h

diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 099e9e1..f176253 100644 (file)
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -22,9 +21,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
 #else
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE           0x00201000
-#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
 #define CONFIG_SPL_PAD_TO              0x40000
 #define CONFIG_SPL_MAX_SIZE            0x28000
 #define RESET_VECTOR_OFFSET            0x27FFC
@@ -35,14 +31,11 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
-#define CONFIG_SPL_NAND_BOOT
 #endif
 
 #ifdef CONFIG_SDCARD
 #define        CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
-#define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST      0x00200000
 #define CONFIG_SYS_MMC_U_BOOT_START    0x00200000
@@ -50,9 +43,7 @@
 #ifndef CONFIG_SPL_BUILD
 #define        CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
-#define CONFIG_SPL_MMC_BOOT
 #endif
 
 #ifdef CONFIG_SPL_BUILD
@@ -77,29 +68,15 @@
 
 #include "t4qds.h"
 
-#ifndef CONFIG_MTD_NOR_FLASH
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
 #if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_SPI_BUS              0
-#define CONFIG_ENV_SPI_CS               0
-#define CONFIG_ENV_SPI_MAX_HZ           10000000
-#define CONFIG_ENV_SPI_MODE             0
 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_ENV_OFFSET              (512 * 0x800)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -205,7 +182,7 @@ unsigned long get_board_ddr_clk(void);
                                | CSPR_PORT_SIZE_8 \
                                | CSPR_MSEL_GPCM \
                                | CSPR_V)
-#define CONFIG_SYS_AMASK3      IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3      IFC_AMASK(64 * 1024)
 #define CONFIG_SYS_CSOR3       0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
@@ -376,12 +353,9 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_SF_DEFAULT_SPEED         10000000
-#define CONFIG_SF_DEFAULT_MODE          0
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN          /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS    50
 #define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS       0xff4000000ull
@@ -420,7 +394,6 @@ unsigned long get_board_ddr_clk(void);
  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  * env, so we got 0x110000.
  */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR        0x110000
 #elif defined(CONFIG_SDCARD)
 /*
@@ -428,10 +401,8 @@ unsigned long get_board_ddr_clk(void);
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR        (512 * 0x820)
 #elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR        (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -441,10 +412,8 @@ unsigned long get_board_ddr_clk(void);
  * slave SRIO or PCIE outbound window->master inbound window->
  * master LAW->the ucode address in master's memory space.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_FMAN_FW_ADDR        0xFFE00000
 #else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR                0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
@@ -452,7 +421,6 @@ unsigned long get_board_ddr_clk(void);
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_TERANETICS
@@ -480,7 +448,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #ifdef CONFIG_FMAN_ENET
-#define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
 #endif
 
@@ -492,7 +459,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_HAS_FSL_DR_USB
 
 #ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33