+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
-#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
+#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x00201000
-#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
-#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
-#define CONFIG_SPL_MMC_BOOT
#endif
#ifdef CONFIG_SPL_BUILD
#include "t4qds.h"
-#ifndef CONFIG_MTD_NOR_FLASH
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 0x800)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_ADDR 0xffe20000
-#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_ENV_IS_NOWHERE)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 0x0
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE 0
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#endif
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
/*
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33