Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[platform/kernel/u-boot.git] / include / configs / T208xQDS.h

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 17176f4..a9835b9 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -12,22 +12,16 @@
 #define __T208xQDS_H
 
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#define CONFIG_MMC
 #define CONFIG_USB_EHCI
 #if defined(CONFIG_ARCH_T2080)
-#define CONFIG_T2080QDS
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SRIO                /* Enable Serial RapidIO Support */
 #define CONFIG_SRIO1           /* SRIO port 1 */
 #define CONFIG_SRIO2           /* SRIO port 2 */
 #elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_T2081QDS
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500            /* BOOKE e500 family */
-#define CONFIG_E500MC          /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV   /* Category E.HV supported */
 #define CONFIG_MP              /* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
@@ -38,10 +32,9 @@
 #endif
 
 #define CONFIG_SYS_FSL_CPC     /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC     CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC     CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_FSL_IFC         /* Enable IFC Support */
 #define CONFIG_FSL_CAAM                /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW         /* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_RAMBOOT_PBL
@@ -49,7 +42,6 @@
 
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x00201000
 #define CONFIG_SPL_TEXT_BASE           0xFFFD8000
 #define CONFIG_SPL_PAD_TO              0x40000
@@ -228,7 +220,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define CONFIG_SYS_SDRAM_SIZE  2048    /* for fixed parameter use */
@@ -600,7 +591,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET     /* need PCIe reset errata */
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
 #endif
 
 /* Qman/Bman */
@@ -711,7 +701,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SATA2_FLAGS         FLAGS_DMA
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
 #endif
 
 /*
@@ -732,8 +721,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif