global: Migrate CONFIG_MXC_UART_BASE to CFG

[platform/kernel/u-boot.git] / include / configs / T104xRDB.h

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index dfad76e..9d04d30 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -20,13 +20,7 @@
 
 #ifdef CONFIG_MTD_RAW_NAND
 #ifdef CONFIG_NXP_ESBC
-#define CONFIG_U_BOOT_HDR_SIZE         (16 << 10)
-/*
- * HDR would be appended at end of image and copied to DDR along
- * with U-Boot image.
- */
-#define CFG_SYS_NAND_U_BOOT_SIZE       ((768 << 10) + \
-                                        CONFIG_U_BOOT_HDR_SIZE)
+#define CFG_SYS_NAND_U_BOOT_SIZE       ((768 << 10) + (16 << 10))
 #else
 #define CFG_SYS_NAND_U_BOOT_SIZE       (768 << 10)
 #endif
@@ -64,9 +58,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CFG_SYS_INIT_L2CSR0            L2CSR0_L2E
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
 
 /*
  *  Config the L3 Cache as L3 SRAM
@@ -136,24 +127,10 @@
 #define CPLD_LBMAP_RESET               0xFF
 #define CPLD_LBMAP_SHIFT               0x03
 
-#if defined(CONFIG_TARGET_T1042RDB_PI)
-#define CPLD_DIU_SEL_DFP               0x80
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define CPLD_DIU_SEL_DFP               0xc0
 #endif
 
-#if defined(CONFIG_TARGET_T1040D4RDB)
-#define CPLD_INT_MASK_ALL              0xFF
-#define CPLD_INT_MASK_THERM            0x80
-#define CPLD_INT_MASK_DVI_DFP          0x40
-#define CPLD_INT_MASK_QSGMII1          0x20
-#define CPLD_INT_MASK_QSGMII2          0x10
-#define CPLD_INT_MASK_SGMI1            0x08
-#define CPLD_INT_MASK_SGMI2            0x04
-#define CPLD_INT_MASK_TDMR1            0x02
-#define CPLD_INT_MASK_TDMR2            0x01
-#endif
-
 #define CFG_SYS_CPLD_BASE      0xffdf0000
 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
 #define CFG_SYS_CSPR2_EXT      (0xf)
@@ -275,9 +252,7 @@
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
 
-#if defined(CONFIG_TARGET_T1042RDB_PI) || \
-       defined(CONFIG_TARGET_T1040D4RDB)       || \
-       defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 /*
  * RTC configuration
  */
@@ -359,36 +334,16 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR             0x03
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR             0x01
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define CFG_SYS_SGMII1_PHY_ADDR             0x02
 #define CFG_SYS_SGMII2_PHY_ADDR             0x03
 #define CFG_SYS_SGMII3_PHY_ADDR             0x01
 #endif
 
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CFG_SYS_RGMII1_PHY_ADDR             0x04
-#define CFG_SYS_RGMII2_PHY_ADDR             0x05
-#else
 #define CFG_SYS_RGMII1_PHY_ADDR             0x01
 #define CFG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
 
-/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#ifdef CONFIG_TARGET_T1040RDB
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR  0x04
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR  0x08
-#else
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR  0x08
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR  0x0c
-#endif
-#endif
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -411,19 +366,11 @@
 #define __USB_PHY_TYPE utmi
 #define RAMDISKFILE    "t104xrdb/ramdisk.uboot"
 
-#ifdef CONFIG_TARGET_T1040RDB
-#define FDTFILE                "t1040rdb/t1040rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB_PI)
-#define FDTFILE                "t1042rdb_pi/t1042rdb_pi.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB)
-#define FDTFILE                "t1042rdb/t1042rdb.dtb"
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define FDTFILE                "t1042rdb/t1040d4rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define FDTFILE                "t1042rdb/t1042d4rdb.dtb"
 #endif
 
-#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+#define        CFG_EXTRA_ENV_SETTINGS                          \
        "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\