Convert CONFIG_PCIE1 et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / T104xRDB.h

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index a56e3bf..8222c67 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -32,21 +32,14 @@
 #endif
 #define CONFIG_SYS_NAND_U_BOOT_DST     0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_START   0x30000000
-#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x30000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x30000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define        CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
 #endif
 
 #ifdef CONFIG_SDCARD
@@ -55,9 +48,6 @@
 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x30000000)
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x30000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define        CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
 #endif
 
 #endif
@@ -71,18 +61,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1                   /* PCIE controller 1 */
-#define CONFIG_PCIE2                   /* PCIE controller 2 */
-#define CONFIG_PCIE3                   /* PCIE controller 3 */
-#define CONFIG_PCIE4                   /* PCIE controller 4 */
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#endif
-#endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -93,8 +71,6 @@
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /*
  *  Config the L3 Cache as L3 SRAM
  */
@@ -118,7 +94,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51
 
 #define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */
@@ -391,26 +366,9 @@
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1               CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS         FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
 /*
 * USB
 */
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
 
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR