#ifdef CONFIG_T1042RDB
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
#endif
+#ifdef CONFIG_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
+#endif
+#ifdef CONFIG_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
+#endif
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SILENT_CONSOLE
+#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
+#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3
+#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
-#ifdef CONFIG_T1042RDB_PI
+
+#if defined(CONFIG_T1042RDB_PI)
#define CPLD_DIU_SEL_DFP 0x80
+#elif defined(CONFIG_T1042D4RDB)
+#define CPLD_DIU_SEL_DFP 0xc0
+#endif
+
+#if defined(CONFIG_T1040D4RDB)
+#define CPLD_INT_MASK_ALL 0xFF
+#define CPLD_INT_MASK_THERM 0x80
+#define CPLD_INT_MASK_DVI_DFP 0x40
+#define CPLD_INT_MASK_QSGMII1 0x20
+#define CPLD_INT_MASK_QSGMII2 0x10
+#define CPLD_INT_MASK_SGMI1 0x08
+#define CPLD_INT_MASK_SGMI2 0x04
+#define CPLD_INT_MASK_TDMR1 0x02
+#define CPLD_INT_MASK_TDMR2 0x01
#endif
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#endif
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
/* Video */
#define CONFIG_FSL_DIU_FB
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define I2C_MUX_CH_DEFAULT 0x8
#endif
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define CONFIG_QE
#define CONFIG_U_QE
#endif
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
+#endif
+
+#ifdef CONFIG_T104XD4RDB
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
+#else
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+#endif
+
+/* Enable VSC9953 L2 Switch driver on T1040 SoC */
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
+#define CONFIG_VSC9953
+#define CONFIG_CMD_ETHSW
+#ifdef CONFIG_T1040RDB
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
+#else
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
+#endif
#endif
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4"
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#ifdef CONFIG_T1042RDB_PI
#define CONFIG_CMD_DATE
#endif
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SETEXPR
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
#endif
/* Hash command with SHA acceleration supported in hardware */
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
#elif defined(CONFIG_T1042RDB)
#define FDTFILE "t1042rdb/t1042rdb.dtb"
+#elif defined(CONFIG_T1040D4RDB)
+#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
+#elif defined(CONFIG_T1042D4RDB)
+#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
#ifdef CONFIG_FSL_DIU_FB