/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#define CONFIG_T1040QDS
#define CONFIG_PHYS_64BIT
+#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
#endif
/* High Level Configuration Options */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
#define CONFIG_MP /* support multiple processors */
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1105)
+#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3
+#endif
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0xf)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED 50000
+#define CONFIG_SYS_FSL_I2C3_SPEED 50000
+#define CONFIG_SYS_FSL_I2C4_SPEED 50000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
#define I2C_MUX_PCA_ADDR 0x77
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_DIU 0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR 0x38
+#define CONFIG_SYS_I2C_DVI_ADDR 0x75
/*
* RTC configuration
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
+#define CONFIG_QE
+#define CONFIG_U_QE
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
+/* Enable VSC9953 L2 Switch driver */
+#define CONFIG_VSC9953
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);"\
+ "fff800000.flash:2m(uboot),9m(kernel),"\
+ "128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
/*
* Environment
*/
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SETEXPR
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
#endif
/*
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1;" \
+ "hwconfig=fsl_ddr:bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
+ "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
+ "bdev=sda3\0"
#define CONFIG_LINUX \
"setenv bootargs root=/dev/ram rw " \
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
-#endif
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff