+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x30001000
-#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define RESET_VECTOR_OFFSET 0x27FFC
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#endif /* CONFIG_RAMBOOT_PBL */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
/* PCIe Boot - Master */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
/*
#endif
#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_SIZE 0x2000
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L3 Cache as L3 SRAM
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_FSL_DDR_INTERACTIVE
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_BAR
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE 0
/*
* General PCIe
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DPAA_FMAN
-#ifdef CONFIG_TARGET_T1024RDB
-#define CONFIG_QE
-#define CONFIG_U_QE
-#endif
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
/*
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
#endif
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_AQUANTIA
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
#endif
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#endif
/*
* Dynamic MTD Partition support with mtdparts
*/
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_FLASH_CFI_MTD
-#endif
/*
* Environment
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*