MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig

[platform/kernel/u-boot.git] / include / configs / T102xRDB.h

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index bd458ff..14f0ce6 100644 (file)
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -14,10 +14,7 @@
 #include <linux/stringify.h>
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
 
-#define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
@@ -89,7 +86,7 @@
 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 /* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS      \
                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
@@ -98,7 +95,6 @@
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
@@ -116,10 +112,6 @@
 #define CONFIG_SYS_DCSRBAR_PHYS                0xf00000000ull
 #endif
 
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM      0
-
 /*
  * DDR Setup
  */
@@ -127,11 +119,9 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x51
 #define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_SDRAM_SIZE   2048
 #endif
 
@@ -171,14 +161,8 @@
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
 
 #ifdef CONFIG_TARGET_T1024RDB
@@ -291,10 +275,6 @@
 #define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NAND_FTIM3
 #endif
 
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
 #define CONFIG_HWCONFIG
 
 /* define to use L1 as initial stack */
@@ -355,9 +335,6 @@
  * General PCIe
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCIE1           /* PCIE controller 1 */
-#define CONFIG_PCIE2           /* PCIE controller 2 */
-#define CONFIG_PCIE3           /* PCIE controller 3 */
 
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -383,8 +360,6 @@
 #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
 /*
@@ -434,8 +409,6 @@
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 
 #define CONFIG_SYS_DPAA_FMAN
-
-#define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -471,7 +444,6 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
 /*
  * Environment Configuration
@@ -497,7 +469,7 @@
        "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
-       "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
+       "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
        "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
        "netdev=eth0\0"                                         \
        "tftpflash=tftpboot $loadaddr $uboot && "               \