Merge remote branch 'u-boot-ppc4xx/master'

[platform/kernel/u-boot.git] / include / configs / SXNI855T.h

diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index a8454d9..3aee45c 100644 (file)
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -146,14 +146,26 @@
 
 #define CFG_DISCOVER_PHY
 
-#define CONFIG_COMMANDS                (CONFIG_CMD_DFL         | \
-                                CFG_CMD_EEPROM         | \
-                                CFG_CMD_JFFS2          | \
-                                CFG_CMD_NAND           | \
-                                CFG_CMD_DATE)
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+
 
 #define CFG_JFFS2_SORT_FRAGMENTS
 
@@ -192,7 +204,7 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_ChipID_UNKNOWN    0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
@@ -226,7 +238,7 @@
  */
 #define        CFG_LONGHELP                    /* undef to save a little memory */
 #define        CFG_PROMPT              "=>"    /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 #else
 #define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
@@ -238,7 +250,7 @@
 #define CFG_MEMTEST_START      0x0100000       /* memtest works on     */
 #define CFG_MEMTEST_END                0x0400000       /* 1 ... 4 MB in DRAM   */
 
-#define CFG_LOAD_ADDR          0x00100000
+#define CFG_LOAD_ADDR          0x00100000
 
 #define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 
@@ -309,7 +321,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif