Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx

[platform/kernel/u-boot.git] / include / configs / SPD823TS.h

diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index 9ad1839..395c7a1 100644 (file)
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -59,15 +59,29 @@
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
-#define CONFIG_COMMANDS \
-((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+#undef CONFIG_CMD_FLASH
+
+
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
 
 /*----------------------------------------------------------------------*/
 #define CONFIG_ETHADDR         00:D0:93:00:01:CB
@@ -82,7 +96,7 @@
  */
 #define CFG_LONGHELP                   /* undef to save memory         */
 #define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
 #else
 #define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
@@ -160,7 +174,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif
 
@@ -307,7 +321,6 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define      CFG_DER 0x2002000F*/
 #define CFG_DER 0
 
 /*
@@ -382,7 +395,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB   204
+#define CFG_MBMR_PTB   204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit    */
 #define CFG_MPTPR_2BK_4K       MPTPR_PTP_DIV16         /* setting for 2 banks  */
@@ -397,9 +410,9 @@
  */
 
 /* 8 column SDRAM */
-#define CFG_MBMR_8COL  ((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-                        MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |   \
-                        MAMR_RLFB_1X    | MAMR_WLFB_1X    | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+                        MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
+                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 
 /*
  * Internal Definitions