/*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#undef CONFIG_EDT32F10
#define CONFIG_SHARP_LQ057Q3DC02
+#define CONFIG_SPLASH_SCREEN
+
#define MPC8XX_FACT 1 /* Multiply by 1 */
#define MPC8XX_XIN 50000000 /* 50 MHz in */
#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
+#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#define CONFIG_BOOTDELAY 0 /* immediate boot */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#undef CONFIG_SCC1_ENET
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#if 0
-#ifdef CONFIG_LCD
-# undef CONFIG_STATUS_LED /* disturbs display */
-#else
-# define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#endif /* CONFIG_LCD */
-#endif
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(50)
-#define CFG_I2C_PWM_ADDR 0x58 /* Power management coprocessor */
-#define CFG_I2C_KBD_ADDR 0x50 /* Keyboard coprocessor */
-#define CFG_I2C_TERM_ADDR 0x49 /* Temperature Sensors */
+#define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */
+#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
+#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_BSP )
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
+#define CFG_DEVICE_NULLDEV 1 /* we need the null device */
+#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */
+
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition
+ * use all the space starting at offset 3MB*/
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00300000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=r360-0"
+#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
+*/
+
+/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
*
*/
-#define CFG_DER 0x2002000F
-/*#define CFG_DER 0*/
+#define CFG_DER 0
/*
* Init Memory Controller:
/*
- * BR1 and OR1 (SDRAM)
+ * BR2 and OR2 (SDRAM)
*
*/
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-#define CFG_PRELIM_OR1_AM 0xF8000000 /* OR addr mask */
+#define CFG_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
OR_SCY_0_CLK | OR_G5LS)
-#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3 and OR3 (CAN Controller)
+ */
+#ifdef CONFIG_CAN_DRIVER
+#define CFG_CAN_BASE 0xC0000000 /* CAN base address */
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA |OR_BI)
+#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V)
+#endif /* CONFIG_CAN_DRIVER */
/*
projects / platform / kernel / u-boot.git / blobdiff