ppc4xx: Use common NS16550 driver for PPC4xx UART

[platform/kernel/u-boot.git] / include / configs / PPChameleonEVB.h

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 44f03dc..f9b2014 100644 (file)
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -191,6 +191,12 @@
 #define CONFIG_SYS_MEMTEST_START       0x0400000       /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 
+#define CONFIG_CONS_INDEX      1       /* Use UART0                    */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK             /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD           691200
 
@@ -542,13 +548,13 @@
  * GPIO0[30]   - EMAC0 input
  * GPIO0[31]   - EMAC1 reject packet as output
  */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000550
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1L       0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1L         0x15555444
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_OSRL          0x40000550
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H       0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555444
 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 #define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 
 /*
@@ -577,17 +583,6 @@
 #define                DIMM_READ_ADDR 0xAB
 #define                DIMM_WRITE_ADDR 0xAA
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register              */
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register       */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register          */
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register    */
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register              */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register            */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register              */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register                 */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                                */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register             */
-
 /* Defines for CPC0_PLLMR1 Register fields */
 #define PLL_ACTIVE             0x80000000
 #define CPC0_PLLMR1_SSCS       0x80000000