/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
* (C) Copyright 2003
* DAVE Srl
*
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_33
+#define CONFIG_PPCHAMELEON_CLK_25
#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
/* Ethernet stuff */
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
+#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
+#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
+#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
- CFG_CMD_PCI )
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_SNTP )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
+#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+/*
+ * nand device 1 on dave (PPChameleonEVB) needs more time,
+ * so we just introduce additional wait in nand_wait(),
+ * effectively for both devices.
+ */
+#define PPCHAMELON_NAND_TIMER_HACK
+
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
+#define NAND_BIG_DELAY_US 25
+#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
+#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
-#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
} \
} while(0)
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
} \
} while(0)
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
} \
} while(0)
+#if 0
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+
+
+
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
#define NAND_WAIT_READY(nand) do { \
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
+#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
+
+/* Reserve 256 kB for Monitor */
+/*
#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN (256 * 1024)
+*/
+
+/* Reserve 320 kB for Monitor */
+#define CFG_FLASH_BASE 0xFFFB0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (320 * 1024)
+
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00400000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
+*/
+
+/* 256 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+ "1792k(user),256k(u-boot);" \
+ "ppchameleonevb-nand:-(nand)"
+*/
+
+/* 320 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+ "1728k(user),320k(u-boot);" \
+ "ppchameleonevb-nand:-(nand)"
+*/
+
#endif /* __CONFIG_H */