Merge branch 'master' into next

[platform/kernel/u-boot.git] / include / configs / PMC440.h

diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 7071ccb..6310cfc 100644 (file)
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -215,12 +215,11 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM        (256)   /* 256MB                        */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE    /* use DDR2 optimization        */
 #endif
-#define CFG_MEM_TOP_HIDE       (4 << 10) /* don't use last 4kbytes     */
-                                       /* 440EPx errata CHIP 11        */
+#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes */
+                                                 /* 440EPx errata CHIP 11 */
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -230,7 +229,6 @@
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
-#define CONFIG_I2C_CMD_TREE    1
 #define CONFIG_I2C_MULTI_BUS   1
 
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -315,6 +313,7 @@
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_IBM_EMAC4_V4    1
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address, See schematics  */
@@ -352,7 +351,6 @@
 
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_DIAG
@@ -360,7 +358,6 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
@@ -436,11 +433,14 @@
 /* Board-specific PCI */
 #define CONFIG_SYS_PCI_TARGET_INIT
 #define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 
 /* PCI identification */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441     /* PCI Device ID: Non-Monarch */
 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440        /* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID       CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH    PCI_CLASS_PROCESSOR_POWERPC
 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH       PCI_CLASS_BRIDGE_HOST
 
@@ -489,8 +489,8 @@
 #endif
 
 /* Memory Bank 1 (RESET) initialization */
-#define CFG_EBC_PB1AP          0x7f817200 //0x03017200
-#define CFG_EBC_PB1CR          (CFG_RESET_BASE | 0x1c000)
+#define CONFIG_SYS_EBC_PB1AP           0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_RESET_BASE | 0x1c000)
 
 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 #define CONFIG_SYS_EBC_PB4AP           0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
@@ -504,7 +504,6 @@
  * NAND FLASH
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
 #define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1 /* nand driver supports mutipl. chips */
 #define CONFIG_SYS_NAND_QUIET_TEST     1