Change all '$(...)' variable references into '${...}'

[platform/kernel/u-boot.git] / include / configs / PM826.h

diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 6668578..6e5e3bb 100644 (file)
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,11 +37,10 @@
 
 #define CONFIG_MPC8260         1       /* This is a MPC8260 CPU        */
 #define CONFIG_PM826           1       /* ...on a PM8260 module        */
+#define CONFIG_CPM2            1       /* Has a CPM2 */
 
 #undef CONFIG_DB_CR826_J30x_ON         /* J30x jumpers on D.B. carrier */
 
-#define        CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
-
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
 
 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
@@ -49,8 +48,8 @@
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
        "bootp; "                                                               \
-       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
-       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
+       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
        "bootm"
 
 /* enable I2C and select the hardware/software driver */
@@ -156,20 +155,26 @@
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 
 #ifdef CONFIG_PCI
-#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | \
-                                CFG_CMD_BEDBUG | \
-                                CFG_CMD_DATE   | \
-                                CFG_CMD_DOC    | \
-                                CFG_CMD_EEPROM | \
-                                CFG_CMD_I2C    | \
-                                CFG_CMD_PCI)
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
+                               CFG_CMD_BEDBUG  | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_DOC     | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_SNTP    )
 #else  /* ! PCI */
-#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | \
-                                CFG_CMD_BEDBUG | \
-                                CFG_CMD_DATE   | \
-                                CFG_CMD_DOC    | \
-                                CFG_CMD_EEPROM | \
-                                CFG_CMD_I2C    )
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
+                               CFG_CMD_BEDBUG  | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_DOC     | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_SNTP    )
 #endif /* CONFIG_PCI */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -220,15 +225,18 @@
 /*-----------------------------------------------------------------------
  * Flash and Boot ROM mapping
  */
-
+#ifdef CONFIG_FLASH_32MB
+#define        CFG_FLASH0_BASE         0x40000000
+#define        CFG_FLASH0_SIZE         0x02000000
+#else
+#define        CFG_FLASH0_BASE         0xFF000000
+#define        CFG_FLASH0_SIZE         0x00800000
+#endif
 #define        CFG_BOOTROM_BASE        0xFF800000
 #define        CFG_BOOTROM_SIZE        0x00080000
-#define        CFG_FLASH0_BASE         0xFF000000
-#define        CFG_FLASH0_SIZE         0x02000000
 #define CFG_DOC_BASE           0xFF800000
 #define CFG_DOC_SIZE           0x00100000
 
-
 /* Flash bank size (for preliminary settings)
  */
 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
@@ -237,8 +245,11 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS    1       /* max num of memory banks      */
+#ifdef CONFIG_FLASH_32MB
+#define CFG_MAX_FLASH_SECT     135     /* max num of sects on one chip */
+#else
 #define CFG_MAX_FLASH_SECT     128     /* max num of sects on one chip */
-
+#endif
 #define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
 
@@ -411,7 +422,7 @@
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR        (SCCR_DFBRG01)
+#define CFG_SCCR        (SCCR_DFBRG00)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
@@ -426,7 +437,6 @@
  * ---- ---     ------- ------  ------
  *  0   60x     GPCM    64 bit  FLASH
  *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
  *
  */
 
@@ -440,7 +450,12 @@
  */
 #define CFG_MIN_AM_MASK        0xC0000000
 
-#define CFG_MPTPR       0x1F00
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.73 uS (64 MHz Bus Clock)
+ */
+#define CFG_MPTPR       0x2000
+#define CFG_PSRT        0x0E
 
 #define CFG_MRS_OFFS   0x00000000
 
@@ -512,7 +527,7 @@
 
 /* Bank 2 - SDRAM
  */
-#define CFG_PSRT        0x0F
+
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
                         BRx_PS_64                      |\