ppc4xx: Enable USB on PLU405 boards

[platform/kernel/u-boot.git] / include / configs / PLU405.h

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 6b16654..4d302ef 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -88,7 +88,10 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
 
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -148,14 +151,16 @@
 
 #define CFG_HZ         1000            /* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING 1       /* add command line history     */
 #define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
 #define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
 
 /* Only interrupt boot if space is pressed */
 /* If a long serial cable is connected but */
 /* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_KEYED  1
+#define CONFIG_AUTOBOOT_PROMPT \
+       "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 #undef CONFIG_AUTOBOOT_DELAY_STR
 #define CONFIG_AUTOBOOT_STOP_STR " "
 
@@ -189,7 +194,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
-#define CONFIG_PCI_HOST        PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_HOST        PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */
 
@@ -205,7 +210,7 @@
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -261,10 +266,10 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define CFG_SDRAM_BASE         0x00000000
-#define CFG_FLASH_BASE         0xFFFC0000
+#define CFG_FLASH_BASE         0xFFFA0000
 #define CFG_MONITOR_BASE       TEXT_BASE
-#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN         (256 * 1024)    /* Reserve 256 kB for malloc()  */
+#define CFG_MONITOR_LEN                (384 * 1024)    /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (384 * 1024)    /* Reserve 256 kB for malloc()  */
 
 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CFG_RAMBOOT           1
@@ -288,6 +293,7 @@
 #define CFG_I2C_SLAVE          0x7F
 
 #define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT24WC08             */
+#define CFG_EEPROM_WREN         1
 
 /* CAT24WC08/16... */
 #define CFG_I2C_EEPROM_ADDR_LEN 1      /* Bytes of address             */
@@ -379,15 +385,16 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH         0x40000550
+#define CFG_GPIO0_OSRH         0x00000550
 #define CFG_GPIO0_OSRL         0x00000110
 #define CFG_GPIO0_ISR1H                0x00000000
 #define CFG_GPIO0_ISR1L                0x15555445
 #define CFG_GPIO0_TSRH         0x00000000
 #define CFG_GPIO0_TSRL         0x00000000
-#define CFG_GPIO0_TCR          0xF7FE0014
+#define CFG_GPIO0_TCR          0x77FE0014
 
 #define CFG_DUART_RST          (0x80000000 >> 14)
+#define CFG_EEPROM_WP          (0x80000000 >> 0)
 
 /*
  * Internal Definitions
@@ -401,7 +408,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
+#if 1
 #define PLLMR0_DEFAULT  PLLMR0_266_133_66_33
 #define PLLMR1_DEFAULT  PLLMR1_266_133_66_33
 #endif
@@ -409,9 +416,19 @@
 #define PLLMR0_DEFAULT  PLLMR0_200_100_50_33
 #define PLLMR1_DEFAULT  PLLMR1_200_100_50_33
 #endif
-#if 1
+#if 0
 #define PLLMR0_DEFAULT  PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT  PLLMR1_133_66_66_33
 #endif
 
+/*
+ * PCI OHCI controller
+ */
+#define CONFIG_USB_OHCI_NEW    1
+#define CONFIG_PCI_OHCI                1
+#define CFG_OHCI_SWAP_REG_ACCESS 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CONFIG_USB_STORAGE     1
+
 #endif /* __CONFIG_H */