Adjust "echo" as a default command
[platform/kernel/u-boot.git] / include / configs / PIP405.h
index 2cd5726..806e95f 100644 (file)
@@ -50,7 +50,6 @@
                        CFG_CMD_PCI     | \
                        CFG_CMD_CACHE   | \
                        CFG_CMD_IRQ     | \
-                       CFG_CMD_ECHO    | \
                        CFG_CMD_EEPROM  | \
                        CFG_CMD_I2C     | \
                        CFG_CMD_REGINFO | \
@@ -69,6 +68,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define         CFG_HUSH_PARSER
 #define         CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************
  ***************************************************************/
 #define SPD_EEPROM_ADDRESS      0x50
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 /**************************************************************
  * Environment definitions
  **************************************************************/
 
 #define CONFIG_BOOTDELAY       5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10     /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME      -10     /XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK    /* check console even if bootdelay = 0 */
 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
+#define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs                    */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define FLASH_SIZE_PRELIM       3  /* maximal flash FLASH size bank #0 */
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR       0xF4000000