Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE references

[platform/kernel/u-boot.git] / include / configs / PIP405.h

diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index b83520d..6e8d7ad 100644 (file)
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -77,7 +77,7 @@
 #define CONFIG_CMD_BSP
 
 
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
 
 #define         CFG_HUSH_PARSER
 #define         CFG_PROMPT_HUSH_PS2 "> "
@@ -95,15 +95,14 @@
 
 #define CFG_I2C_EEPROM_ADDR    0x53
 #define CFG_I2C_EEPROM_ADDR_LEN        2
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
+#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
 
 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
 #define CFG_EEPROM_PAGE_WRITE_BITS 6   /* The Atmel 24C128/256 has     */
                                        /* 64 byte page write mode using*/
                                        /* last 6 bits of the address   */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE   /* enable Page write */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10      /* and takes up to 10 msec */
 
 
@@ -123,7 +122,7 @@
 #define CONFIG_BOOTDELAY       5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME      -10     /XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check console even if bootdelay = 0 */
 
 
 #define CONFIG_BOOTCOMMAND     "diskboot 400000 0:1; bootm" /* autoboot command                */
@@ -252,7 +251,7 @@
 #define CFG_TEMP_STACK_OCM     1
 #define CFG_OCM_DATA_ADDR      0xF0000000
 #define CFG_OCM_DATA_SIZE      0x1000
-#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
 #define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE       /* End of On Chip SRAM         */
 #define CFG_GBL_DATA_SIZE      64              /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -281,7 +280,6 @@
  ***********************************************************/
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                1       /* PHY address                  */
-#define CONFIG_CS8952_PHY      1       /* its a CS8952 PHY             */
 /************************************************************
  * RTC
  ***********************************************************/