/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2004
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
* High Level Configuration Options
* (easy to change)
*/
-
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PCI405 1 /* ...on a PCI405 board */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 0
-#define CONFIG_PREBOOT \
- "crc32 f0207004 ffc 0;" \
- "if cmp 0 f0207000 1;" \
- "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
- "else;echo Old CRC is bad;fi"
-#endif
+#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
#undef CONFIG_BOOTARGS
-#if 1
-#define CONFIG_BOOTCOMMAND \
- "bootm fffc0000"
-#else
-#define CONFIG_BOOTCOMMAND \
- "mw.l 0 ffffffff; mw.l 4 ffffffff;" \
- "while cmp 0 4 1; do echo Waiting for Host...;done;" \
- "bootm 400000"
-#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mem_linux=14336k\0" \
+ "optargs=panic=0\0" \
+ "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
+ "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
+
+#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
+/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
+#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
+#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
+#if 0 /* test-only */
#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#else
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#endif
/*
* Internal Definitions