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configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs
[platform/kernel/u-boot.git] / include / configs / P2041RDB.h
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index e196f3c..65d3dfa 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -37,7 +38,6 @@
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
 #define CONFIG_PCIE3                   /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_SRIO
@@ -46,34 +46,14 @@
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN           /* RMan */
 
-#define CONFIG_ENV_OVERWRITE
-
 #if defined(CONFIG_SPIFLASH)
-       #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
-       #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
-       #define CONFIG_ENV_SECT_SIZE            0x10000
 #elif defined(CONFIG_SDCARD)
        #define CONFIG_FSL_FIXED_MMC_LOCATION
-       #define CONFIG_SYS_MMC_ENV_DEV          0
-       #define CONFIG_ENV_SIZE                 0x2000
-       #define CONFIG_ENV_OFFSET               (512 * 1658)
-#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_SIZE                        CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET              (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_ADDR                0xffe20000
-#define CONFIG_ENV_SIZE                0x2000
-#elif defined(CONFIG_ENV_IS_NOWHERE)
-#define CONFIG_ENV_SIZE                0x2000
-#else
-       #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
-                       - CONFIG_ENV_SECT_SIZE)
-       #define CONFIG_ENV_SIZE         0x2000
-       #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 #endif
 
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(unsigned long dummy);
+#include <linux/stringify.h>
 #endif
 #define CONFIG_SYS_CLK_FREQ    get_board_sys_clk(0)
 
@@ -87,14 +67,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP                64      /* number of TLB1 entries */
-#endif
-
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY     /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x00400000
 
 /*
  *  Config the L3 Cache as L3 SRAM
@@ -222,7 +195,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
                               | OR_FCM_TRLX \
                               | OR_FCM_EHTR)
 
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
@@ -286,14 +259,20 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM4        (CONFIG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED       400000
 #define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET      0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED      400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET     0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER  0
+#endif
+#define CONFIG_SYS_I2C_FSL
+
 
 /*
  * RapidIO
@@ -354,60 +333,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
-#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS    10
@@ -459,7 +399,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_FMAN_FW_ADDR        (512 * 1680)
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FMAN_FW_ADDR        (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
@@ -476,14 +416,23 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#endif
-
 #ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+#endif
 
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
 #endif /* CONFIG_PCI */
@@ -528,10 +477,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
 
 /*
- * Command line configuration.
- */
-
-/*
 * USB
 */
 #define CONFIG_HAS_FSL_DR_USB
Domain: System / Kernel;