Merge tag 'next-20220328' of https://source.denx.de/u-boot/custodians/u-boot-video...

[platform/kernel/u-boot.git] / include / configs / P2041RDB.h

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index bf8a92c..40898a6 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -36,7 +36,6 @@
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
 #define CONFIG_PCIE3                   /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1                   /* SRIO port 1 */
@@ -50,18 +49,14 @@
 #endif
 
 #ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
 #include <linux/stringify.h>
 #endif
-#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk(0)
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
@@ -97,7 +92,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define SPD_EEPROM_ADDRESS     0x52
@@ -137,9 +131,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CPLD_BASE_PHYS         CPLD_BASE
 #endif
 
-#define CONFIG_SYS_BR3_PRELIM  (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM  0xffffeff7      /* 32KB but only 4k mapped */
-
 #define PIXIS_LBMAP_SWITCH     7
 #define PIXIS_LBMAP_MASK       0xf0
 #define PIXIS_LBMAP_SHIFT      4
@@ -148,7 +139,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Write Timeout (ms) */
@@ -185,21 +175,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
                               | OR_FCM_SCY_1 \
                               | OR_FCM_TRLX \
                               | OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif /* CONFIG_NAND_FSL_ELBC */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -371,7 +346,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_FSL_SATA_V2
 
 #ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE     2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1               CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS         FLAGS_DMA
@@ -397,7 +371,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
 
 #define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME                "FM1@DTSEC1"
 #endif
 
 /*
@@ -413,7 +386,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_HAS_FSL_MPH_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 
@@ -438,7 +410,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin
 
 #define __USB_PHY_TYPE utmi
@@ -464,32 +435,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
        "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
        "bdev=sda3\0"
 
-#define HDBOOT                                 \
-       "setenv bootargs root=/dev/$bdev rw "           \
-       "console=$consoledev,$baudrate $othbootargs;"   \
-       "tftp $loadaddr $bootfile;"                     \
-       "tftp $fdtaddr $fdtfile;"                       \
-       "bootm $loadaddr - $fdtaddr"
-
-#define NFSBOOTCOMMAND                 \
-       "setenv bootargs root=/dev/nfs rw "     \
-       "nfsroot=$serverip:$rootpath "          \
-       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-       "console=$consoledev,$baudrate $othbootargs;"   \
-       "tftp $loadaddr $bootfile;"             \
-       "tftp $fdtaddr $fdtfile;"               \
-       "bootm $loadaddr - $fdtaddr"
-
-#define RAMBOOTCOMMAND                         \
-       "setenv bootargs root=/dev/ram rw "             \
-       "console=$consoledev,$baudrate $othbootargs;"   \
-       "tftp $ramdiskaddr $ramdiskfile;"               \
-       "tftp $loadaddr $bootfile;"                     \
-       "tftp $fdtaddr $fdtfile;"                       \
-       "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND             HDBOOT
-
 #include <asm/fsl_secure_boot.h>
 
 #endif /* __CONFIG_H */