#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
- BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM \
- ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
- | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-
#define CONFIG_FSL_CPLD
#define CPLD_BASE 0xffdf0000 /* CPLD registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_LBMAP_SHIFT 4
#define PIXIS_LBMAP_ALTBANK 0x40
-#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Nand Flash */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*