/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
+#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
CONFIG_RAMBOOT_TEXT_BASE)
#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
*/
/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
/*
* This board doesn't have a promjet connector.
* However, it uses commone corenet board LAW and TLB.
* It is necessary to use the same start address with proper offset.
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_FSL_CPLD
#define PIXIS_LBMAP_SHIFT 4
#define PIXIS_LBMAP_ALTBANK 0x40
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CFG_SYS_NAND_BASE 0xffa00000
| OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
-
-#define CONFIG_HWCONFIG
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
+#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
+#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
+#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
+#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
+#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
+#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
-#define CONFIG_SYS_TBIPA_VALUE 8
+#define CFG_SYS_TBIPA_VALUE 8
#endif
#ifdef CONFIG_MMC
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
/*
* Environment Configuration
*/
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_UBOOTPATH u-boot.bin
#define __USB_PHY_TYPE utmi
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
projects / platform / kernel / u-boot.git / blobdiff