#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_DDR3 1
#undef CONFIG_FSL_DDR_INTERACTIVE
-// #define CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */
+/* ECC will be enabled based on perf_mode environment variable */
+/* #define CONFIG_DDR_ECC */
+
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
-//#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
/* Default settings for "stable" mode */
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000