powerpc/85xx: Read board switch settings on p1_p2_rdb

[platform/kernel/u-boot.git] / include / configs / P1_P2_RDB.h

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index bf34740..6f2088e 100644 (file)
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -50,20 +50,21 @@
 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
+#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_TEXT_BASE           0xf8f82000
 #endif /* CONFIG_NAND_SPL */
 #endif
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD          1
-#define CONFIG_SYS_TEXT_BASE           0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS    0xf8fffffc
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH                1
-#define CONFIG_SYS_TEXT_BASE           0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS    0xf8fffffc
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -177,8 +178,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory map
  *
  * 0x0000_0000 0x3fff_ffff     DDR                     1G cacheablen
- * 0xa000_0000 0xbfff_ffff     PCI Express Mem         1G non-cacheable
- * 0xffc2_0000 0xffc5_ffff     PCI IO range            256K non-cacheable
+ * 0x8000_0000  0xbfff_ffff    PCI Express Mem         1G non-cacheable
+ * 0xffc0_0000  0xffc3_ffff    PCI IO range            256k non-cacheable
  *
  * Localbus cacheable (TBD)
  * 0xXXXX_XXXX 0xXXXX_XXXX     SRAM                    YZ M Cacheable
@@ -263,7 +264,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP                ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 
 /* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8       /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
@@ -293,7 +294,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_VSC7385_BASE_PHYS   CONFIG_SYS_VSC7385_BASE
 
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_BR2_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
+                                                       | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM  (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
                                OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
                                OR_GPCM_EHTR | OR_GPCM_EAD)
@@ -344,7 +346,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_NOPROBES        {{0,0x29}}      /* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET          0x3000
@@ -357,10 +358,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x52
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_BUS_NUM      1
 
+#define CONFIG_SYS_I2C_PCA9557_ADDR    0x18
+
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_RTC_DS1337_NOOSC
 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
@@ -369,27 +372,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #if defined(CONFIG_PCI)
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_NAME          "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc30000
-#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc30000
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play */