+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#endif
/* High Level Configuration Options */
-#define CONFIG_MP /* support multiple processors */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1"
#endif