powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig

[platform/kernel/u-boot.git] / include / configs / P1022DS.h

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 582dd36..4b2eb65 100644 (file)
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -13,7 +13,6 @@
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_SPL_MAX_SIZE            (128 * 1024)
 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
@@ -21,8 +20,6 @@
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_MMC_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
@@ -32,7 +29,6 @@
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_SPL_MAX_SIZE            (128 * 1024)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
@@ -40,8 +36,6 @@
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_SPI_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
@@ -53,12 +47,11 @@
 
 #ifdef CONFIG_NAND
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
-#define CONFIG_SPL_TEXT_BASE           0xf8f81000
+#define CONFIG_TPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
@@ -67,7 +60,6 @@
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TEXT_BASE           0xff800000
 #define CONFIG_SPL_MAX_SIZE            4096
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xf8f80000
@@ -77,7 +69,6 @@
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_TPL_PAD_TO              0x20000
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 /* High Level Configuration Options */
@@ -90,7 +81,6 @@
 #define CONFIG_PCIE2                   /* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3                   /* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #define CONFIG_ENABLE_36BIT_PHYS
@@ -213,15 +203,15 @@
 #define CONFIG_SYS_MAX_FLASH_SECT      1024
 
 #ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #endif
 #endif
 
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Nand Flash */
@@ -262,7 +252,6 @@
 
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 
 #define CONFIG_FSL_NGPIXIS
@@ -306,7 +295,6 @@
 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE     0xf8f81000
 #define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (108 << 10)
 #define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
@@ -391,15 +379,6 @@
 #define CONFIG_SYS_EEPROM_BUS_NUM      1
 
 /*
- * eSPI - Enhanced SPI
- */
-
-#define CONFIG_HARD_SPI
-
-#define CONFIG_SF_DEFAULT_SPEED                10000000
-#define CONFIG_SF_DEFAULT_MODE         0
-
-/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
@@ -489,7 +468,6 @@
 
 #define CONFIG_TSECV2
 
-#define CONFIG_MII                     /* MII PHY management */
 #define CONFIG_TSEC1           1
 #define CONFIG_TSEC1_NAME      "eTSEC1"
 #define CONFIG_TSEC2           1
@@ -510,18 +488,11 @@
 /*
  * Dynamic MTD Partition support with mtdparts
  */
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_FLASH_CFI_MTD
 
 /*
  * Environment
  */
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_SPI_BUS     0
-#define CONFIG_ENV_SPI_CS      0
-#define CONFIG_ENV_SPI_MAX_HZ  10000000
-#define CONFIG_ENV_SPI_MODE    0
 #define CONFIG_ENV_SIZE                0x2000  /* 8KB */
 #define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE   0x10000