#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#endif
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
#endif
#endif
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
#define CFG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* CFI for NOR Flash */
#endif
/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CFG_SYS_BAUDRATE_TABLE \
/* eSPI - Enhanced SPI */
#endif
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#endif /* CONFIG_TSEC_ENET */
-
#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
* Environment Configuration
*/
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"loadaddr=1000000\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \