MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig

[platform/kernel/u-boot.git] / include / configs / P1010RDB.h

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index aea744c..8492a64 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -114,44 +114,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-/* DDR3 Controller Settings */
-#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
-#define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR       0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR   0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL      0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR         0x00000000
-#define CONFIG_SYS_DDR_RCW_1           0x00000000
-#define CONFIG_SYS_DDR_RCW_2           0x00000000
-#define CONFIG_SYS_DDR_CONTROL         0xc70c0008      /* Type = DDR3  */
-#define CONFIG_SYS_DDR_CONTROL_2       0x24401000
-#define CONFIG_SYS_DDR_TIMING_4                0x00000001
-#define CONFIG_SYS_DDR_TIMING_5                0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3_800    0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800    0x0FA888CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800    0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800      0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/* settings for DDR3 at 667MT/s */
-#define CONFIG_SYS_DDR_TIMING_3_667            0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_667            0x00110004
-#define CONFIG_SYS_DDR_TIMING_1_667            0x5d59e544
-#define CONFIG_SYS_DDR_TIMING_2_667            0x0FA890CD
-#define CONFIG_SYS_DDR_CLK_CTRL_667            0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667              0x00441210
-#define CONFIG_SYS_DDR_MODE_2_667              0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667            0x0a280000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_667       0x8675F608
-
 #define CONFIG_SYS_CCSRBAR                     0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW            CONFIG_SYS_CCSRBAR
 
@@ -175,7 +137,6 @@ extern unsigned long get_sdram_size(void);
 /* NOR Flash on IFC */
 
 #define CONFIG_SYS_FLASH_BASE          0xee000000
-#define CONFIG_SYS_MAX_FLASH_SECT      256     /* 32M */
 
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
@@ -201,15 +162,9 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
 /* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* NAND Flash on IFC */
 #define CONFIG_SYS_NAND_BASE           0xff800000
@@ -342,12 +297,6 @@ extern unsigned long get_sdram_size(void);
                                        FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3           0x0
 
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000 /* stack in RAM */
 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000 /* End of used area in RAM */
@@ -402,10 +351,6 @@ extern unsigned long get_sdram_size(void);
 
 /* I2C EEPROM */
 #if defined(CONFIG_TARGET_P1010RDB_PB)
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_EEPROM_BUS_NUM      0
 #define MAX_NUM_PORTS                  9 /* for 128Bytes EEPROM */
 #endif
 /* enable read and write access to EEPROM */
@@ -483,7 +428,6 @@ extern unsigned long get_sdram_size(void);
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20) /* Increase max gunzip size */
 
 /*
  * Environment Configuration