Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u...

[platform/kernel/u-boot.git] / include / configs / P1010RDB.h

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 6024cce..60e8904 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -16,7 +16,6 @@
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE           0xD0001000
 #define CONFIG_SPL_PAD_TO              0x18000
 #define CONFIG_SPL_MAX_SIZE            (96 * 1024)
 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (512 << 10)
@@ -24,22 +23,19 @@
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_MMC_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
 #else
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE                   0xD0001000
 #define CONFIG_SPL_PAD_TO                      0x18000
 #define CONFIG_SPL_MAX_SIZE                    (96 * 1024)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (512 << 10)
@@ -47,22 +43,18 @@
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (96 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_SPI_BOOT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
 #endif
 #endif
 
-#ifdef CONFIG_NAND
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_MTD_RAW_NAND
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 
-#define CONFIG_SPL_TEXT_BASE           0xFFFFE000
 #define CONFIG_SPL_MAX_SIZE            8192
 #define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
 #define CONFIG_SPL_RELOC_STACK         0x00100000
@@ -70,15 +62,13 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x00200000 - CONFIG_SPL_MAX_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #else
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
-#define CONFIG_SPL_TEXT_BASE           0xD0001000
+#define CONFIG_TPL_TEXT_BASE           0xD0001000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (576 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
@@ -88,7 +78,6 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TEXT_BASE           0xff800000
 #define CONFIG_SPL_MAX_SIZE            8192
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xD0000000
@@ -98,7 +87,6 @@
 #define CONFIG_SPL_PAD_TO      0x20000
 #define CONFIG_TPL_PAD_TO      0x20000
 #define CONFIG_SPL_TARGET      "u-boot-with-spl.bin"
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 #endif
 
@@ -111,7 +99,9 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
@@ -125,7 +115,6 @@
 #define CONFIG_PCIE2                   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 /*
@@ -184,7 +173,6 @@
 #define CONFIG_DDR_CLK_FREQ    66666666 /* DDRCLK on P1010 RDB */
 #define CONFIG_SYS_CLK_FREQ    66666666 /* SYSCLK for P1010 RDB */
 
-#define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -322,10 +310,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 
 /* CFI for NOR Flash */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* NAND Flash on IFC */
 #define CONFIG_SYS_NAND_BASE           0xff800000
@@ -403,7 +388,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NAND_DDR_LAW                11
 
 /* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
@@ -464,7 +449,6 @@ extern unsigned long get_sdram_size(void);
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
        defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
@@ -500,7 +484,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (128 << 10)
 #define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR                0xD0000000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
@@ -574,14 +558,11 @@ extern unsigned long get_sdram_size(void);
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
-#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
-#define CONFIG_SF_DEFAULT_SPEED                10000000
-#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #endif
 
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII                     /* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
 #define CONFIG_TSEC1   1
 #define CONFIG_TSEC1_NAME      "eTSEC1"
@@ -648,36 +629,16 @@ extern unsigned long get_sdram_size(void);
 #if defined(CONFIG_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV         0
-#define CONFIG_ENV_SIZE                        0x2000
-#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_SPI_BUS     0
-#define CONFIG_ENV_SPI_CS      0
-#define CONFIG_ENV_SPI_MAX_HZ  10000000
-#define CONFIG_ENV_SPI_MODE    0
-#define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE   0x10000
-#define CONFIG_ENV_SIZE                0x2000
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR           (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ENV_SIZE                (16 * 1024)
 #define CONFIG_ENV_RANGE       (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 #endif
 #endif
-#define CONFIG_ENV_OFFSET      (1024 * 1024)
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_ADDR                        (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE                        0x2000
-#else
-#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */