rename CFG_ENV macros to CONFIG_ENV

[platform/kernel/u-boot.git] / include / configs / NETTA.h

diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 19743c0..805b82a 100644 (file)
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -60,11 +60,11 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
 
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
+       "tftpboot; "                                                            \
        "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
        "bootm"
@@ -93,23 +93,24 @@
 
 #define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 
-#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
+#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
 #define        FEC_ENET                1       /* eth.c needs it that way... */
 #undef  CFG_DISCOVER_PHY               /* do not discover phys */
 #define CONFIG_MII             1
+#define CONFIG_MII_INIT                1
 #define CONFIG_RMII            1       /* use RMII interface */
 
 #if defined(CONFIG_NETTA_ISDN)
 #define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                1       /* phy address of FEC1 */
+#define CONFIG_FEC1_PHY                1       /* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #undef  CONFIG_ETHER_ON_FEC2
 #else
 #define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                8       /* phy address of FEC1 */
+#define CONFIG_FEC1_PHY                8       /* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #define CONFIG_ETHER_ON_FEC2   1
-#define CONFIG_FEC2_PHY                1       /* phy address of FEC2 */
+#define CONFIG_FEC2_PHY                1       /* phy address of FEC2 */
 #define CONFIG_FEC2_PHY_NORXERR 1
 #endif
 
@@ -219,16 +220,16 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
-#define        CFG_ENV_IS_IN_FLASH     1
-#define CFG_ENV_SECT_SIZE      0x10000
+#define        CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SECT_SIZE   0x10000
 
-#define        CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_OFFSET         0
-#define        CFG_ENV_SIZE            0x4000
+#define        CONFIG_ENV_ADDR         (CFG_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_OFFSET              0
+#define        CONFIG_ENV_SIZE         0x4000
 
-#define CFG_ENV_ADDR_REDUND    (CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_OFFSET_REDUND  0
-#define CFG_ENV_SIZE_REDUND    CFG_ENV_SIZE
+#define CONFIG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_OFFSET_REDUND       0
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -295,27 +296,27 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -325,19 +326,19 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  80000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  50000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -495,8 +496,6 @@
 #define        BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 #define BOOTFLAG_WARM  0x02            /* Software reboot                      */
 
-#define CONFIG_ARTOS                   /* include ARTOS support */
-
 #define CONFIG_LAST_STAGE_INIT         /* needed to reset the damn phys */
 
 /***********************************************************************************************************
@@ -620,7 +619,7 @@
 /****************************************************************/
 
 /* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
 #define CFG_NAND_BASE                  NAND_BASE
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
@@ -632,7 +631,7 @@
 #define ADDR_COLUMN            1
 #define ADDR_PAGE              2
 #define ADDR_COLUMN_PAGE       3
-#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_ChipID_UNKNOWN    0x00
 #define NAND_MAX_FLOORS                1
 #define NAND_MAX_CHIPS         1