Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boards

[platform/kernel/u-boot.git] / include / configs / NETPHONE.h

diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 9dadaa8..bb3d19d 100644 (file)
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -49,8 +49,8 @@
 
 /* #define CONFIG_XIN           10000000 */
 #define CONFIG_XIN              50000000
-#define MPC8XX_HZ              120000000
-/* #define MPC8XX_HZ            66666666 */
+/* #define MPC8XX_HZ           120000000 */
+#define MPC8XX_HZ               66666666
 
 #define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ
 
@@ -67,8 +67,8 @@
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
        "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
        "bootm"
 
 #define CONFIG_AUTOSCRIPT
@@ -82,7 +82,15 @@
 #define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
 #define CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 
-#define CONFIG_BOOTP_MASK              (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
 
 #undef CONFIG_MAC_PARTITION
 #undef CONFIG_DOS_PARTITION
@@ -105,20 +113,22 @@
 
 #define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
 
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL | \
-                               CFG_CMD_NAND    | \
-                               CFG_CMD_DHCP    | \
-                               CFG_CMD_PING    | \
-                               CFG_CMD_MII     | \
-                               CFG_CMD_CDP       \
-                               )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
 
 #define CONFIG_BOARD_EARLY_INIT_F      1
 #define CONFIG_MISC_INIT_R
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
 /*
  * Miscellaneous configurable options
  */
@@ -128,7 +138,7 @@
 #define CFG_HUSH_PARSER        1
 #define CFG_PROMPT_HUSH_PS2    "> "
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 #else
 #define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
@@ -220,7 +230,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif
 
@@ -336,16 +346,18 @@
  *-----------------------------------------------------------------------
  * Set clock output, timebase and RTC source and divider,
  * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
  */
 
 #define SCCR_MASK      SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR       (SCCR_TBS     | \
+#define CFG_SCCR       (/* SCCR_TBS    | */ SCCR_CRQEN | \
                         SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
                         SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
                         SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR       (SCCR_TBS     | \
+#define CFG_SCCR       (/* SCCR_TBS    | */ SCCR_CRQEN | \
                         SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
                         SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
                         SCCR_DFALCD00)
@@ -489,8 +501,11 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
 
 #define CFG_MAX_NAND_DEVICE    1
 
@@ -571,6 +586,11 @@
 
 /*****************************************************************************/
 
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
 #if CONFIG_NETPHONE_VERSION == 1
 #define STATUS_LED_BIT         0x00000008              /* bit 28 */
 #elif CONFIG_NETPHONE_VERSION == 2