#define CONFIG_MPC834x 1
#define CONFIG_MPC8343 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
/*
* U-Boot memory configuration
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/* LB sdram refresh timer, about 6us */
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 3
-#define PCI_66M
+#define CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66666667
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_BOOTP_SEND_HOSTNAME
/* USB */
+#define CONFIG_SYS_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/*
* Environment
#define CONFIG_CMD_PCI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_USB
+#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_HRCW_LOW 0x0
#define CONFIG_SYS_HRCW_HIGH 0x0
#define CONFIG_SYS_SCCR_TSEC1CM 1
#define CONFIG_SYS_SCCR_TSEC2CM 1
-#define CONFIG_SYS_SICRH 0x1fff8003
+#define CONFIG_SYS_SICRH 0x1fef0003
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#define MV_FPGA_SIZE 0
#define MV_KERNEL_ADDR 0xff810000
#define MV_INITRD_ADDR 0xffb00000
-#define MV_SOURCE_ADDR 0xff804000
-#define MV_SOURCE_ADDR2 0xff806000
+#define MV_SCRIPT_ADDR 0xff804000
+#define MV_SCRIPT_ADDR2 0xff806000
#define MV_DTB_ADDR 0xff808000
#define MV_INITRD_LENGTH 0x00400000
#define MV_DTB_ADDR_RAM 0x00600000
#define MV_INITRD_ADDR_RAM 0x01000000
-#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
- then source ${autoscr_addr}; \
- else source ${autoscr_addr2}; \
+#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
+ then source ${script_addr}; \
+ else source ${script_addr2}; \
fi;"
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
"fpga=0\0" \
"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \
- "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \
+ "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \