Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 17dac6c..efe0313 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007, 2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -21,14 +21,14 @@
 
 #define        CONFIG_SYS_TEXT_BASE    0xfff00000
 
-#define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
 
 /* video */
-#undef CONFIG_VIDEO
-
-#ifdef CONFIG_VIDEO
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR    (CONFIG_SYS_CCSRBAR + 0x2c000)
+#define CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
@@ -88,8 +88,6 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
 #define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
 
-#define CONFIG_SYS_DIU_ADDR            (CONFIG_SYS_CCSRBAR+0x2c000)
-
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -108,7 +106,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS     0x51    /* CTLR 0 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
 #define CONFIG_SYS_SDRAM_SIZE  256             /* DDR is 256MB */
@@ -276,6 +274,7 @@
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 /* controller 1, Base address 0xa000 */
+#define CONFIG_SYS_PCIE1_NAME          "ULI"
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
@@ -284,6 +283,7 @@
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /* 1M */
 
 /* controller 2, Base Address 0x9000 */
+#define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
@@ -492,9 +492,6 @@
 #define CONFIG_WATCHDOG                        /* watchdog enabled */
 #define CONFIG_SYS_WATCHDOG_FREQ       5000    /* Feed interval, 5s */
 
-/*DIU Configuration*/
-#define DIU_CONNECT_TO_DVI             /* DIU controller connects to DVI encoder*/
-
 /*
  * Miscellaneous configurable options
  */