Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index a53953c..e9371a2 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -24,7 +24,7 @@
 #define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
 
 /* video */
-#define CONFIG_VIDEO
+#undef CONFIG_VIDEO
 
 #if defined(CONFIG_VIDEO)
 #define CONFIG_CFB_CONSOLE
@@ -42,6 +42,7 @@
 #define CONFIG_PCIE1           1       /* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2           1       /* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
+#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
 
@@ -54,6 +55,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
 
+#define CONFIG_HIGH_BATS       1       /* High BATs supported & enabled */
 #define CONFIG_ALTIVEC         1
 
 /*
@@ -70,10 +72,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
 #define CONFIG_MISC_INIT_R             1
 
-#undef CFG_DRAM_TEST                   /* memory test, takes time */
 #define CFG_MEMTEST_START      0x00200000      /* memtest region */
 #define CFG_MEMTEST_END                0x00400000
-#define CFG_ALT_MEMTEST
 
 /*
  * Base addresses -- Note these are effective addresses where the
@@ -113,7 +113,7 @@
 #if 0 /* TODO */
 #define CFG_DDR_CS0_BNDS       0x0000000F
 #define CFG_DDR_CS0_CONFIG     0x80010202      /* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH    0x00000000
+#define CFG_DDR_TIMING_3       0x00000000
 #define CFG_DDR_TIMING_0       0x00260802
 #define CFG_DDR_TIMING_1       0x3935d322
 #define CFG_DDR_TIMING_2       0x14904cc8
@@ -140,11 +140,11 @@
 #endif
 #endif
 
-#define CFG_ID_EEPROM
-#ifdef CFG_ID_EEPROM
 #define CONFIG_ID_EEPROM
-#endif
-#define ID_EEPROM_ADDR         0x57
+#define CFG_I2C_EEPROM_NXID
+#define CFG_ID_EEPROM
+#define CFG_I2C_EEPROM_ADDR     0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
 
 
 #define CFG_FLASH_BASE         0xf0000000 /* start of FLASH 128M */
@@ -192,7 +192,7 @@
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 #define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
 
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
@@ -314,6 +314,7 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_CMD_NET
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
 
 #define CONFIG_ULI526X
 #ifdef CONFIG_ULI526X
@@ -328,7 +329,7 @@
 #define CONFIG_USB_KEYBOARD    1
 #define CFG_DEVICE_DEREGISTER
 #define CFG_USB_EVENT_POLL     1
-#define CFG_USB_OHCI_SLOT_NAME         "ohci_pci"
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 #define CFG_OHCI_SWAP_REG_ACCESS       1
 
@@ -484,7 +485,8 @@
 #endif
 
 
-#undef CONFIG_WATCHDOG                 /* watchdog disabled */
+#define CONFIG_WATCHDOG                        /* watchdog enabled */
+#define CFG_WATCHDOG_FREQ      5000    /* Feed interval, 5s */
 
 /*DIU Configuration*/
 #define DIU_CONNECT_TO_DVI             /* DIU controller connects to DVI encoder*/